The manufacture of semiconductor devices such as Static Random Access Memory (SRAM) structures can be challenging due to the need to etch a variety of films in a precise and cost effective manner. A conventional technique employed to manufacture SRAM structures includes the use of a trilayer patterning stack, as is depicted in FIGS. 1A-1C. Such a trilayer patterning stack includes a silicon-containing layer that functions as an anti-reflective layer to modulate the reflectivity of the patterning stack during pattern imaging, and also functions as a hard mask during pattern transfer.
As illustrated in FIG. 1A, a high-κ dielectric layer 12 is formed over the silicon substrate 10. A titanium nitride layer 14 is formed over high-κ dielectric layer 12, an amorphous silicon layer 16 is formed over titanium nitride layer 14, and a hard mask layer 18 is formed over amorphous silicon layer 16. A trilayer patterning stack, comprising sequentially an optical dispersive layer 20, a silicon anti-reflective coating (ARC) layer 22, and a photoresist layer 24 defining a pattern, is then formed over hard mask layer 18.
Etching is then performed to transfer the pattern to the hard mask layer 18, which results in the structure shown in FIG. 1B. Then, a stripping step is performed in an effort to remove the remaining optical dispersive layer 20 and the silicon anti-reflective coating layer 22. However, stripping does not consistently result in the removal of all of the material from the silicon anti-reflective coating layer 22. As shown in FIG. 1C, a residue 26 from the silicon anti-reflective coating layer typically remains after the stripping step when using such a conventional trilayer patterning stack.
It is extremely difficult to completely remove the antireflective layer, e.g., a silicon ARC layer, when transferring the pattern to the hard mask layer. The remaining silicon ARC material within the hard mask openings causes blockages during subsequent of a conductive layer, e.g., a silicon substrate, and consequential conductive paths causing short circuiting resulting in device malfunction and reduced yields. This problem becomes increasingly acute as the thickness of the hard mask layer is reduced to meet the continuously increasing demand for high density devices. This problem becomes even more acute in double patterning double etch processes using a thin hard mask.
A need therefore exists for methodology enabling the fabrication of semiconductor devices comprising accurately formed patterns, particularly conductive patterns, with high reliability and increased yield, and for the resulting devices. A particular need exists for methodology enabling the accurate formatting of fine conductive patterns without forming short circuits, thereby increasing manufacturing yields.